1. Field of the Invention
The present invention relates to a refresh counter circuit used for refresh operation in a semiconductor memory such as a DRAM (dynamic random access memory), and a control method for the refresh operation, and, more particularly, relates to a technical field for, for example, a refresh counter circuit by which the refresh operation is controlled in a longer period than that of normal operation in order to realize further less power consumption, wherein the refresh counter circuit is used for refresh operation in a memory array including a normal area and a parity area.
2. Related Art
Conventionally, refresh operation has been required to be controlled in a longer period than that of normal operation in order to realize further less power consumption in a data holding state of a DRAM. Thereby, there has been proposed a configuration in which an error correction function using parity bits are installed in the DRAM to correct bit errors which are increased as the period of the refresh operation is made longer. In the DRAM with the above-described configuration, it is required to provide a normal area which stores data bits input to a memory device, and a parity area which stores the above-described parity bits, and a refresh counter which can be applied to the both normal and parity areas during refresh operation is demanded to be prepared. For example, a configuration disclosed in Japanese Patent Laid-Open Application No. 2004-118938 can be given as one example.
In the configuration disclosed in Laid-Open Application No. 2004-118938, a refresh counter corresponding to a 13-bit address space for row addresses in the memory device is included, and a switch is controlled in such a way that all the 13 bits are connected during refresh operation in the normal area, and, on the other hand, eight bits among 13 bits are connected during refresh operation in the parity area. Thereby, a circuit can be used in common for a circuit for the normal area and that for the parity area to control the refresh operation without enlarging the circuit scale of the refresh counter.
Moreover, the configuration and the size of the address space for the normal area are different from those for the parity area in the configuration of Japanese Laid-Open Application No. 2004-118938, wherein the refresh counter performs count-up operation in the normal area and the parity area. In this case, a preferable configuration is that an area discriminating circuit, which generates a signal discriminating the normal area from the parity area, is added to, for example, a final stage of the refresh counter, and an area in which the count operation is performed can be decided.
In the above-described conventional configuration, a counter portion for five bits among counter used in the normal area becomes an indefinite area in the parity area. Accordingly, when the operation mode requiring refresh operation in the parity area is temporarily stopped while the operation mode is executed (an operation such as Exit operation and Entry operation from the later-described burst refresh process, or a power-off state), it is required to avoid the subsequent restarting of refresh operation in the parity area as the indefinite area remains unclear. As one measure for the above requirement, it is considered that stopping of the operation mode is disabled while the refresh operation is executed in the parity area.
However, the above-described operation mode is considered to include long-time processing with comparatively large loading, such as encode process before the refresh operation in a longer period. Moreover, the operation mode is also required to have a lower internal-clock speed in order to realize less power consumption. In this case, as delay in the subsequent operation is caused by an operation in which stopping of the operation mode is disabled during refresh operation in the parity area, it is preferable from the viewpoint of rapid control to have a specification in which stopping of the operation mode is enabled at any time. When the above-described stopping of the operation mode is caused, a problem is that one measure is required to avoid a situation in which a refresh counter is set in an indefinite area of the parity area at the subsequent restarting of the operation mode.